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| NLSF308 Quad 2-Input AND Gate The NLSF308 is an advanced high speed CMOS 2-input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features http://onsemi.com * * FUNCTION TABLE Inputs A L L H H B L H L H Output Y L L L H NLSF308 = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NLSF308MNR2 NLSF308MNR2G Package QFN-16 QFN-16 (Pb-Free) Shipping 3000 / Tape & Reel 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2006 1 May, 2006 - Rev. 4 CCC CCC CCC * * * * * * * * * * * High Speed: tPD = 4.3 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Function Compatible with Other Standard Logic Families QFN-16 Package Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model; > 2000 V; Machine Model; > 200 V Chip Complexity: 24 FETs or 6 Equivalent Gates Pb-Free Package is Available* 1 QFN-16 MN SUFFIX CASE 485G MARKING DIAGRAM 16 1 NLSF 308 ALYW G G Publication Order Number: NLSF308/D IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I III I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIII I I IIIII Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII A3 Y3 GND Y2 A1 B4 VCC B1 RECOMMENDED OPERATING CONDITIONS MAXIMUM RATINGS Input Rise and Fall Time Operating Temperature DC Output Voltage DC Input Voltage DC Supply Voltage Storage Temperature Power Dissipation in Still Air DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage B3 A3 B2 A2 A1 B1 B4 A4 9 4 8 3 15 16 13 12 Figure 1. LOGIC DIAGRAM Parameter Parameter 10 7 5 1 Y3 Y2 Y1 Y4 Y = AB http://onsemi.com VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V NLSF308 2 NC B2 A2 Y1 1 4 3 2 Figure 2. PIN ASSIGNMENT (QFN-16) 16 5 Symbol Symbol VCC VCC Vout Vout Tstg tr, tf ICC IOK Iout Vin Vin PD TA IIK NLSF308 MN Package 15 (Top View) 6 14 7 Min -0.5 to VCC + 0.5 -40 2.0 0 0 0 0 -65 to + 150 -0.5 to + 7.0 -0.5 to + 7.0 Value 13 450 -20 50 25 20 8 + 85 Max VCC 5.5 5.5 100 20 10 Y4 12 A4 11 NC 9 B3 ns/V Unit Unit mW mA mA mA mA C C V V V V V V NLSF308 II IIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIII II I I II I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIII IIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I II I I I I I I I I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I I I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII IIIIII I III II I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIII I III II I III I I I I I I I I I I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III IIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII DC ELECTRICAL CHARACTERISTICS Parameter Test Conditions Symbol VIH VIL VCC V TA = 25C Typ TA = - 40 to 85C Min Max Min Max Unit V V V Minimum High-Level Input Voltage 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 1.50 VCC x 0.7 1.50 VCC x 0.7 Maximum Low-Level Input Voltage 0.50 VCC x 0.3 0.50 VCC x 0.3 Minimum High-Level Output Voltage Vin = VIH or VIL IOH = -50 mA VOH 1.9 2.9 4.4 2.0 3.0 4.5 1.9 2.9 4.4 Vin = VIH or VIL IOH = -4 mA, IOH = -8 mA Vin = VIH or VIL IOL = 50 mA Vin = VIH or VIL IOL = 4 mA IOL = 8 mA 2.58 3.94 2.48 3.80 Maximum Low-Level Output Voltage VOL 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 V 0.36 0.36 0.44 0.44 Maximum Input Leakage Current Maximum Quiescent Supply Current Vin = 5.5 V or GND Vin = VCC or GND 0 to 5.5 5.5 0.1 2.0 1.0 20.0 mA mA AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) Parameter TA = 25C Typ 6.2 8.7 4.3 5.8 4 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 Max 10.5 14.0 7.0 9.0 10 Test Conditions Symbol tPLH, tPHL Min Max Unit ns Maximum Propagation Delay, A or B to Y VCC = 3.3 0.3 V, CL = 15 pF, CL = 50 pF VCC = 5.0 0.5 V, CL = 15 pF, CL = 50 pF 8.8 12.3 5.9 7.9 10 Maximum Input Capacitance Cin pF Typical @ 25C, VCC = 5.0 V 18 Power Dissipation Capacitance (Note 1) CPD pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25C Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Symbol VOLP VOLV VIHD VILD Typ 0.3 -0.3 Max 0.8 -0.8 3.5 1.5 Unit V V V V http://onsemi.com 3 NLSF308 VCC A or B 50% GND tPLH tPHL Y 50% VCC Figure 3. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit http://onsemi.com 4 NLSF308 PACKAGE DIMENSIONS 16 PIN QFN CASE 485G-01 ISSUE C D A B PIN 1 LOCATION E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.15 C 0.15 C 0.10 C TOP VIEW 16 X 0.08 C SIDE VIEW A1 C 16X L 5 NOTE 5 4 16X K 1 12 16X b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CC CC CC (A3) D2 e 8 9 16 13 A SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L EXPOSED PAD E2 e http://onsemi.com 5 NLSF308/D |
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